The redundant cell adder

This paper describes the design of the 56-bit signifcand adder for the Advanced Micro Devices Am290.501 microprocessor. This is a 1 pm design rule CMOS realization of a high performance RISC microprocessor that implements IEEE Standard 754 floating point arithmetic. To achieve an add time of under 4 ns for the 56-bit significand and to avoid multistage pipelines which signijlcantly impair compiler eficiency, a redundant cell adder has been developed. This new design is a key to realizing the high performance for floating point arithmetic that is achieved by the Am29050 microprocessor.